DATE Workshop on Machine Learning for CAD

DATE Workshop on Machine Learning for CAD

Workshop: Machine Learning for CAD

Held at DATE Conference, Florence, March 29, 2019

Organizers: Joerg Henkel, KIT; Hussam Amrouch, KIT; Marilyn Wolf, Georgia Tech

This workshop focuses on machine learning methods for all aspects of CAD and electronic system design. Advances in machine learning (ML) over the past half-dozen years have revolutionized the effectiveness of ML for a variety of applications. However, design processes present challenges that require parallel advances in ML and CAD as compared to traditional ML applications such as image classification. As such, the purpose of the workshop is to discuss, define and provide a roadmap for the special needs for ML for CAD where CAD is broadly defined as design time techniques as well as run-time techniques. The results of the workshop are planned for publication in form of a special issue at a major ACM or IEEE journal/magazine.

Topics of interest to this workshop include but are not limited to:

  • ML approaches to logic design.
  • Machine learning for physical design.
  • ML for analog design.
  • Machine learning methods to predict aging and reliability.
  • Labeled and unlabeled data in ML for CAD.
  • ML for power and thermal management.
  • ML techniques for resource management in manycores.

The workshop will include both submitted and invited speakers.  Submissions (1-3 pages, no formatting requirements) should be sent by Friday, December 18 to wolf@ece.gatech.edu

Workshop schedule:

Time Label Session
07:30 W07.1 Registration Desk Opens
08:30 W07.2

Design Space Exploration using Machine Learning

08:30-09:00: Ulf Schlichtmann, TU Munich, Title: Machine Learning Approaches for Efficient Design Space Exploration of Application-specific NoCs.

09:00-09:30: Nicolas Ventroux, CEA-LIST, Title: Machine Learning for Design Space Exploration of CPS.

09:30-10:00: Rajesh Gupta, UC San Diego,Title: TBA

10:00 W07.3 Morning Coffee Break
10:30 W07.4

Design for Reliability using Machine Learning

10:30-11:00: Rolf Drechsler, Univ. of Bremen, Title: Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques.

11:00-11:30: Siddharth Garg, New York University, Title: ML4TPU: Machine Learning for Energy Efficient and Reliable ML Hardware.

11:30-12:00: Kai-Chiang, National Chiao Tung University, Title: Learning-based methodologies for assessing chip health in terms of aging and reliability.

12:00 W07.5 Lunch Break
13:00 W07.6

Design-Time and Run-Time Machine Learning Techniques for SoCs

13:00-13:30: Paul Franzon, North Carolina State University, Title: Designing Your Circuits with Robots.

13:30-14:00: Krishnendu Chakrabarty, Duke University, Title: Predictive Analytics for Run-Time Anomaly Detection and Failure Prediction in Complex Core Routers.

14:30-15:00: Dimitrios Soudris, Univ. of Athens, Title: A Methodology for Application Implementation onto 3-D FPGAs.

14:30 W07.7 Afternoon Coffee Break
15:00 W07.8

Machine Learning for Circuit Modeling

15:00-15:30: Georges Gielen, KU Leuven

Title: AI learning techniques in design and test of analog integrated circuits

15:30-16:00: Norbert When, TU Kaiserslautern,

Title: Modeling of DRAM Behavior with Recurrent Neural Networks

16:00-16:15: (Poster) Lukas Sekanina and Zdenek Vasicek

Title: Machine Learning in Logic Synthesis

16:15-16:30: (Poster) Huiyuan Song, Title: Fast FPGA Routing Algorithm using Graph Neural Network

16:30 W07.9

Panel: Where Do We Go From Here?

Panelists: Paul Franzon, Rajesh Gupta, Nicholas Ventroux, Norbert Wehn

Moderator: Marilyn Wolf

17:30 W07.10 Workshop Wrap-up
18:30

Joint dinner with discussion of future plans (buy-your-own-meal)

Location: Ristorante Buca Mario

For more information contact Marilyn Wolf wolf@ece.gatech.edu